Principal Engineer DSP PHY Digital Design

Principal Engineer DSP PHY Digital Design

#WeAreIn for jobs that impact everyone's life.

Build the future nobody’s dreamed of yet... are you ready to rethink the impossible?

As a Principal Engineer DSP PHY Digital Design in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?

Your Role

Key responsibilities in your new role

• Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams
• RTL Design and Verification
• Develop equalization and adaptation algorithms for wireline channels (e.g., FFE/DFE, adaptive filtering), including fixed-point considerations
• Design and implement timing recovery/synchronization blocks (CDR, tracking loops), including jitter tolerance and stability/latency tradeoffs
• Contribute to detection and coding / FEC integration: soft-information interfaces, performance/complexity tradeoffs, and linkKPIs
• Build bit-true / fixed-point models and reference implementations primarily in C++ and MATLAB (Python optional, not core)
• Define verification metrics and stress tests (BER/FER, convergence time, corner cases) and partner with DV to ensure coverage
• Support silicon bring-up and lab debug: correlate model ↔ silicon, root-cause issues, and iterate on algorithms/specs
• Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions

Your Profile

Qualifications and skills to help you succeed

• B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field
• Strong fundamentals in digital communications and DSP, including probability/statistics
• Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling
• Strong C++ and MATLAB skills for algorithm development, modeling, and analysis

Preferred qualifications

• Experience with automotive Ethernet PHY/SerDes constraints (robustness, low latency, interoperability, EMI resilience)
• Familiarity with ADC-based receiver architectures and calibration concepts
• Experience translating algorithms into RTL-friendly specs (throughput/latency budgeting, memory/compute sizing, state-machine behavior)
• Knowledge of link startup/training / autoneg concepts and system validation
• Exposure to standards work (e.g., IEEE 802.3) or cross-company technical leadership

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.

We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.